In integrated circuit design, the engineer may sometimes desire to incorporate circuits of different logic families into the same integrated circuit. For example, a design may include a CMOS (complementary metal oxide silicon) circuit which must use the output from an ECL-like (emitter-coupled logic) circuit to perform additional functions. Due to the inherent differences in signal characteristics of the logic families, a conversion must take place at the interface of the two logic family circuits. The present invention is concerned with the conversion of an ECL-like signal typically having characteristics of low swing and large common mode range.
one conventional circuit for ECL-like signal to CMOS signal conversion uses current mirrors, an example of which is shown in FIG. 1. Conventional circuit 10 receives ECL-like signals IN.sub.-- X and IN.sub.-- Y at the gates of pMOS 13 and 12, respectively. In operation, if input signal IN.sub.-- Y is low (and input signal IN.sub.-- X is high, since IN.sub.-- X and IN.sub.-- Y are complementary of one another), then pMOS 12 is turned on, and node 15 is pulled high to approximately V.sub.CC. This in turn switches nMOS 16 on, which pulls node 17 to ground or low. Node 17 is coupled to the gate inputs of a pMOS 18 and an nMOS 19, which in effect forms an inverter. Therefore, the OUT signal from the conversion circuit 10 is inverted to high. A feedback path is formed to couple the output signal OUT to node 20 or the gates of a pMOS 22 and an nMOS 23 interconnected to function as an inverter. The output of the inverter formed by pMOS 22 and nMOS 23, node 21, is coupled to the input of another inverter composed of pMOS 24 and nMOS 25, the output of which is coupled to node 17. Therefore, the high OUT signal is converted to low by MOSFET pair 22 and 23, and then inverted again by MOSFET pair 24 and 25 to high. This effectively pulls node 17 back up.
There are at least three problems associated with conventional circuit 10. First, circuit 10 receives both input signals IN.sub.-- X and IN.sub.-- Y at the gates of two pMOS 13 and 12, respectively. Therefore, because the common mode range of ECL-like input signals IN.sub.-- X and IN.sub.-- Y can be near V.sub.CC, circuit 10 would not function properly if the low level of ECL-like input signals IN.sub.-- X and IN.sub.-- Y is too high to turn pMOS 12 and 13 on. For example, if V.sub.CC is five volts, then the "low" level of IN.sub.-- X and IN.sub.-- Y has to be less than or equal to four volts, or one volt below the V.sub.CC voltage level in order for pMOS 12 and 13 to respond. As a result, low ECL-like signals that are too high to be detected by pMOS 12 and 13 are simply ignored.
A second problem arises from the peculiarity of ECL-like signals which results in high and extremely variable power consumption. High power consumption results if input signals IN.sub.-- X and IN.sub.-- Y are not truly complementary and the high level signals are at too low a voltage level, which may cause both input MOSFETS 12 and 13 to be on simultaneously. To overcome this problem additional circuitry is required to match the high and low voltage levels of IN.sub.-- X and IN.sub.-- Y to the threshold voltage levels of pMOS 12 and 13 over a predetermined temperature range. However, the voltage level matching function is typically not performed because of the time delay and addition to circuit size involved.
A third problem arises from the variance of the threshold voltage level of pMOS 12 and 13 over temperature and process variations. For example, as temperature rises, the threshold voltage of the MOSFETS decreases, leading to an increase in current flowing through a "weaker" component. Additionally, the threshold voltage of MOSFETS may vary greatly with weak and strong processing, thus directly affecting the operations of circuit 10.
Therefore, a need has arisen for a conversion circuit and method which receive at least one input signal having characteristics typical of an ECL signal, and convert it to at least one output signal having characteristics typical of a CMOS signal, that substantially eliminate the above-described problems associated with prior converters. Additionally, it is desirable to provide an ECL-like signal to CMOS signal conversion circuit that produces a two-phase output.